1. Technical Field
The present invention relates to a multi-level dynamic memory device having an open bit line structure and a method of driving the same, and more particularly, to a multi-level dynamic memory device that is highly integrated and a method of driving the same.
2. Description of the Related Art
In recent years, various methods of storing a large amount of data in a limited wafer have been developed. Due to sophisticated lithographic methods and apparatuses, a large number of memory cells can be fabricated within a small wafer. Another method stores one or more bits in one memory cell, thereby realizing an increase in the integration level of a dynamic memory device per unit area. This is generally known as a “multi-level dynamic memory device.”
A conventional multi-level dynamic memory device has been developed on the basis of a folded bit line structure. In the folded bit line structure, since both a bit line and a complementary bit line are located in the same memory cell block, the amount of coupling noise generated between the bit line and a word line is equal to the amount of coupling noise generated between the complementary bit line and the word line. This common-mode noise can be eliminated by a differential amplification operation of a sense amplifier.
However, in the folded bit line structure, it is difficult to reduce the size of a memory cell to less than 8 F2/bit. Here, “F” denotes the minimum feature size, that is, a minimum design rule in which a patterning process can be performed. For this reason, a new structure capable of improving the integration level of the multi-level dynamic memory device is required.